San Jose, California, Oct. 31, 2018 (GLOBE NEWSWIRE) — Andes Technology Corporation, a leading supplier of small gate count, low-power and high performance 32/64-bit embedded CPU cores today announced the debut of RISC-V CON on Tuesday November 13, at the Hyatt Regency Santa Clara. A highlight of the event will be the giveaway of over 100 RISC-V software development kits (SDKs). The SDKs consists of a GOWIN Semiconductor processor board with GOWIN’s Arora® GW2A-18 FPGA containing Andes RISC-V core. The SDKs also contain the comprehensive and industrial-strength AndeSight™ integrated development environment (IDE), which is specialized for this SDK and will be available for download from the GOWIN website for programming and debug.
The conference will begin with the keynote presentation from Linley Gwennap, Founder of The Linley Group, Inc. “Roadmap Directions for the RISC-V Architecture.” At 11:00 Linley will also moderate the panel “Is RISC-V Ready for Your Design?” Shichin Ouyang, MediaTek Director of Technology will describe “RISC-V from MediaTek’s Perspective.” Andes CTO & Senior VP Dr. Charlie Su will detail “Comprehensive RISC-V Solutions for Diversified SoCs” and Andes President Frankwell Lin will present “Unleashing Chip Design Barrier with RISC-V.” GOWIN Semiconductor concludes the morning program by detailing the “RISC-V Microprocessor Implementation for FPGA Solutions.”
After lunch, the conference gets down to the business of RISC-V application development. Andes Technology begins with “Ecosystem and Solutions for AIoT.” XtremeEDA next provides “Thoughts on Hierarchical SoC Verification,” and Faraday describes “Designing RISC-V SoC based on Faraday Solution.” Hex Five Security, Inc. will demonstrate “Trusted Execution Environments on RISC-V.” Imperas Software follows presenting “Building a RISC-V Virtual Platform for Rapid Embedded Software Development.” And Andes Technology will conclude with “Andes Software Solutions for RISC-V,” detailing the AndeSight™ IDE available for the GOWIN board.
About RISC-V CON
RISC-V CON is the first RISC-V conference aimed at SoC developers designing on open-source ISA and software. It will be held on November 13th at the Santa Clara Hyatt Regency Hotel beginning at 9:00 AM. Andes Technology and GOWIN Semiconductor will be providing attendees RISC-V SDKs. Each SDK comprises a GOWIN board with GW2A-18 FPGA containing Andes RISC-V core and Andes AICE-MINI+ linking USB to JTAG for software debug. Registration still available at this link. Complete conference information available at this link.
About Andes Technology Corporation
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores, including the rising star RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2017, the cumulative amount of SoCs containing Andes’ CPU IP reaches 2.5 billion. To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expanded its product line and provides a total solution of RISC-V, the RISC-V series as V5 families processors cores include 32/64-bit N25/NX25 for general purpose, N25F/NX25F for floating-point intensive applications and A25/AX25 for Linux-based applications. For more information about Andes Technology, please visit the company home page.