Here’s why we believe in RISC-V
The end of Moore’s Law Creates Opportunity
When the physicists and chemists were delivering 2x the transistors every 18 months, semiconductors were a big company game. This created consolidation around two primary ISAs – ARM and x86.
However, Moore’s law is now broken – and its now taking 20 years to double transistor count. This is happening at the same time as two key trends in semis that need dramatic improvements in price-performance curves – machine learning (ML) and the Internet of Things (IoT).
ML creates a nearly unlimited demand for processing resources and IoT grows the number of tiny edge devices into the 10s of billions – all of which need low cost and low power.
General purpose compute can’t address these problems as it has no more scaling path – thus the only way to address these needs is with architecture. Specifically – there are three primary approaches that the industry must adopt:
- More to more efficient programming languages -> C is 50x more efficient than Python.
- The problem is software engineering efficiency and security.
- A line of Python does 5-10x more than a line of C and programmers can write lines of code at a relatively fixed rate.
- Lower level languages such as C require programmers to actively manage memory – this opens up a vast attack surface as mistakes in memory allocation expose systems to stack overflow, heap spray and many other forms of attack.
- Specific workloads need to move off general purpose processors and on to hardware accelerators – be they GPUs, FPGAs or hardware blocks.
- The price / performance improvement here is massive – 10-30x – however doing this on FPGAs or GPUs requires a large effort and it does not apply equally to all workload types.
- Hardware architectures need to get refactored around application requirements.
- This is where RISC-V comes in.
The end of Moore’s law means that processor architecture is in a state of disruption where small companies can innovate and add value again – from the gate level to the application level.
The Brilliance of RISC-V – Specialization without Fragmentation
What RISC-V allows is a common base set of instructions (ISA) that are universally supported and a toolchain that is able to handle both the base ISA and pass through customized instructions that a SoC architect can define.
This allows companies like Hex Five to develop a solution like MultiZone™ Security that will work everywhere, while still enabling SoC architects to customize the processor architecture – stages, cache sizes, hardware accelerators – or even create custom instructions to solve specific application issues without breaking compatibility and causing fragmentation.
In the ARM world you can do this with an architecture license (for ~$5M per core type), but when you make changes you also need to take ownership of the toolchain and supporting your developer community. This has proven too much of a burden for even the largest companies to bear and they have given up on custom instructions. This is ARM’s Achilles’ heel.
The Path for RISC-V Adoption
The Linley Group presented a vision of RISC-V adoption at the most recent Andes RISC-V CON on Nov 13, 2018. It goes like this:
- RISC-V displaces custom in-house ISAs that OEMs have developed for peripheral functions (NVIDIA, HP, Qualcomm, etc.)
- AI Accelerators and small / low power applications adopt and apply RISC-V for their workloads to advance the price-performance curve.
- Vertical OEMs with their own SoC capabilities like Western Digital fully convert to RISC-V – look for more of these announcements at the RISC-V Summit in Dec
- Finally – mass market MCUs and MPUs begin to displace ARM in its core markets
The full presentation is available here : Linley Group – Andes RISC-V CON 11/13/18
This process will take more than 10 years; but the disruption it creates up and down the supply chain allows startups to innovate and grow in a way that is not possible on legacy architectures like ARM and x86.