Hex Five is excited to collaborate with Dr. Sandro Pinto on the first Secure IoT Stack for RISC-V which will be
presented at Embedded World in Nuremburg, Germany on Feb 26-27, 2019. This demonstration will detailed
in sessions on Feb 26 and 27th and will be on display at the wolfSSL booth, Hall 4 / Booth 421.
Germany on Feb 26-27. https://www.embedded-world.eu/program.html
SAN JOSE, Calif., Nov. 9, 2018 /PRNewswire/ — Hex Five Security, Inc., the creator of MultiZone™ Security, Andes Technology Corporation and GOWIN Semiconductor Corp announce a collaboration to enable MultiZoneTM Security, the first Trusted Execution Environment for RISC-V on the Andes N(X)25 RISC-V Cores, which is part of 25-series, with the GOWIN GW-2A Family of FPGAs.
Redwood Shores, CA – Nov 1, 2018 /PRNewswire/ – Hex Five Security, Inc, the creator of MultiZone™ Security, the first trusted execution environment for RISC-V, today announced the formation of the Hex Five Strategic Advisory Board, an esteemed group of technical and business leaders chosen to counsel the company on achieving its goal of making RISC-V the most secure processor platform.
Andes RISC-V CON Debuts at Hyatt Regency Santa Clara November 13; Linley Group, MediaTek, Andes, Faraday, GOWIN, Imperas Software, Hex Five, and XtremeEDA to Detail RISC-V Technology Advance
Oct 31, 2018
Andes and GOWIN providing attendees 100+ RISC-V SDK Boards; Conference Presentations Will Describe RISC-V Program Development and Debug
San Jose, California, Oct. 31, 2018 (GLOBE NEWSWIRE) — Andes Technology Corporation, a leading supplier of small gate count, low-power and high performance 32/64-bit embedded CPU cores today announced the debut of RISC-V CON on Tuesday November 13, at the Hyatt Regency Santa Clara.
Trusted Execution Environments (TEEs) such as Arm TrustZone, while well-intentioned, present challenges for engineers. First, they doesn’t allow for partitioning between many sensitive functions within a secure domain, and, perhaps more importantly, they can be very difficult to use. Don Barnetson of Hex-Five discusses TEEs and multi-zone security, a new technology for the RISC-V ISA that enables limitless partitions, each with its own set of resources. And, it has minimal impact on existing development processes and tools.
Arms race: SiFive, Hex Five build code safe houses for RISC-V chips
Sept 10, 2018
Those developing custom CPUs can now tap a TrustZone-ish trusted execution environment
If you’ve been looking at SiFive’s RISC-V-based chip technology and thinking, y’know what, it’s missing an Arm TrustZone-style element to run sensitive code, well, here’s some good news.
And if you’re just into processor design and checking out alternatives to Arm CPU cores, then this may be some interesting news.
SiFive helps organizations turn semiconductor designs based on the open-source RISC-V instruction set architecture (ISA) into chips. On Monday, it announced it has integrated Hex Five Security’s MultiZone Security trusted execution environment (TEE) into its Freedom SDK.
Hex-Five Adds MultiZone™ Security Trusted Execution Environment to SiFive DesignShare Program
Sept 10, 2018
Enabling RISC-V Developers to a Robust Trusted Execution Environment without any changes to hardware or software.
SAN MATEO, Calif. – September 10, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today welcomed Hex Five Security, maker of MultiZone™ Security – the first Trusted Execution Environment (TEE) for RISC-V, to the growing SiFive Software Ecosystem. Through the partnership, SiFive will incorporate MultiZone™ Security into its Freedom SDK for easy adoption by SiFive customers seeking a Trusted Execution Environment.
Hex-Five Announces General Availability of MultiZone™ Security – the First Trusted Execution Environment for RISC-V
Sept 5, 2018
Enabling developers to implement best practices of security through separation without any changes to hardware or software.
REDWOOD CITY, Calif. – Sept 5, 2018 – Hex-Five Security, today announces general availability of MultiZone™ Security – the first Trusted Execution Environment (TEE) for RISC-V providing developers with a critical building block of hardware enforced, policy-based security through separation without the need for any hardware changes.